URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] - Rev 28

Rev	Log message	Author	Age	Path
28	TDO and TDO Enable signal are separated into two signals.	mohor	8381d 01h	/
27	Warnings from synthesys tools fixed.	mohor	8395d 02h	/
26	Warnings from synthesys tools fixed.	mohor	8395d 02h	/
25	trst signal is synchronized to wb_clk_i.	mohor	8395d 23h	/
24	CRC changed so more thorough testing is done.	mohor	8397d 00h	/
23	Trace disabled by default.	mohor	8403d 03h	/
22	Register length fixed.	mohor	8403d 03h	/
21	CRC is returned when chain selection data is transmitted.	mohor	8403d 23h	/
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8405d 02h	/
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8417d 02h	/
18	Reset signals are not combined any more.	mohor	8419d 11h	/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8443d 01h	/
16	bs_chain_o port added.	mohor	8445d 00h	/
15	bs_chain_o added.	mohor	8445d 02h	/
14	Document updated.	mohor	8445d 23h	/
13	Signal names changed to lowercase.	mohor	8446d 02h	/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8447d 02h	/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8467d 22h	/
10	First official release 1.0.	mohor	8472d 02h	/
9	Working version. Few bugs fixed, comments added.	mohor	8472d 02h	/