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Rev Log message Author Age Path
31 trst synchronization is not needed and was removed. mohor 8211d 17h /
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.
mohor 8222d 21h /
29 Document revised and put tp better form. mohor 8226d 10h /
28 TDO and TDO Enable signal are separated into two signals. mohor 8258d 18h /
27 Warnings from synthesys tools fixed. mohor 8272d 19h /
26 Warnings from synthesys tools fixed. mohor 8272d 19h /
25 trst signal is synchronized to wb_clk_i. mohor 8273d 16h /
24 CRC changed so more thorough testing is done. mohor 8274d 17h /
23 Trace disabled by default. mohor 8280d 20h /
22 Register length fixed. mohor 8280d 20h /
21 CRC is returned when chain selection data is transmitted. mohor 8281d 16h /
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8282d 19h /
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8294d 19h /
18 Reset signals are not combined any more. mohor 8297d 04h /
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.
mohor 8320d 18h /
16 bs_chain_o port added. mohor 8322d 17h /
15 bs_chain_o added. mohor 8322d 19h /
14 Document updated. mohor 8323d 16h /
13 Signal names changed to lowercase. mohor 8323d 19h /
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.
mohor 8324d 19h /

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