URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] - Rev 32

Rev	Log message	Author	Age	Path
32	Stupid bug that was entered by previous update fixed.	mohor	8205d 05h	/
31	trst synchronization is not needed and was removed.	mohor	8205d 06h	/
30	IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in not filled-in. Tested in hw.	mohor	8216d 10h	/
29	Document revised and put tp better form.	mohor	8219d 23h	/
28	TDO and TDO Enable signal are separated into two signals.	mohor	8252d 07h	/
27	Warnings from synthesys tools fixed.	mohor	8266d 08h	/
26	Warnings from synthesys tools fixed.	mohor	8266d 08h	/
25	trst signal is synchronized to wb_clk_i.	mohor	8267d 05h	/
24	CRC changed so more thorough testing is done.	mohor	8268d 06h	/
23	Trace disabled by default.	mohor	8274d 09h	/
22	Register length fixed.	mohor	8274d 09h	/
21	CRC is returned when chain selection data is transmitted.	mohor	8275d 05h	/
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8276d 08h	/
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8288d 08h	/
18	Reset signals are not combined any more.	mohor	8290d 17h	/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8314d 07h	/
16	bs_chain_o port added.	mohor	8316d 07h	/
15	bs_chain_o added.	mohor	8316d 08h	/
14	Document updated.	mohor	8317d 05h	/
13	Signal names changed to lowercase.	mohor	8317d 08h	/