OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] - Rev 35

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
35 Dbg support datasheet added to cvs. mohor 8172d 08h /
34 Product brief added to cvs. mohor 8173d 01h /
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8178d 06h /
32 Stupid bug that was entered by previous update fixed. mohor 8179d 05h /
31 trst synchronization is not needed and was removed. mohor 8179d 06h /
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.
mohor 8190d 10h /
29 Document revised and put tp better form. mohor 8193d 23h /
28 TDO and TDO Enable signal are separated into two signals. mohor 8226d 07h /
27 Warnings from synthesys tools fixed. mohor 8240d 08h /
26 Warnings from synthesys tools fixed. mohor 8240d 08h /
25 trst signal is synchronized to wb_clk_i. mohor 8241d 05h /
24 CRC changed so more thorough testing is done. mohor 8242d 06h /
23 Trace disabled by default. mohor 8248d 09h /
22 Register length fixed. mohor 8248d 09h /
21 CRC is returned when chain selection data is transmitted. mohor 8249d 05h /
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8250d 08h /
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8262d 08h /
18 Reset signals are not combined any more. mohor 8264d 17h /
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.
mohor 8288d 07h /
16 bs_chain_o port added. mohor 8290d 06h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.