OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] - Rev 64

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
64 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7764d 16h /
63 Three more chains added for cpu debug access. simons 7764d 16h /
62 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7792d 15h /
61 Lapsus fixed. simons 7792d 15h /
60 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7792d 16h /
59 Reset value for riscsel register set to 1. simons 7792d 16h /
58 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7792d 17h /
57 Multiple cpu support added. simons 7792d 17h /
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 8059d 14h /
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 8059d 14h /
54 This commit was manufactured by cvs2svn to create tag 'rel_2'. 8059d 15h /
53 Trst active high. Inverted on higher layer. mohor 8059d 15h /
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 8059d 15h /
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 8087d 03h /
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 8087d 04h /
49 This commit was manufactured by cvs2svn to create tag 'sdram_test_working'. 8242d 15h /
48 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8242d 15h /
47 mon_cntl_o signals that controls monitor mux added. mohor 8242d 15h /
46 Asynchronous reset used instead of synchronous. mohor 8250d 21h /
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8257d 17h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.