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Rev Log message Author Age Path
67 Lower two address lines must be always zero. simons 7740d 05h /
66 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7741d 05h /
65 WB_CNTL register added, some syncronization fixes. simons 7741d 05h /
64 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7761d 05h /
63 Three more chains added for cpu debug access. simons 7761d 05h /
62 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7789d 05h /
61 Lapsus fixed. simons 7789d 05h /
60 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7789d 06h /
59 Reset value for riscsel register set to 1. simons 7789d 06h /
58 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7789d 07h /
57 Multiple cpu support added. simons 7789d 07h /
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 8056d 03h /
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 8056d 03h /
54 This commit was manufactured by cvs2svn to create tag 'rel_2'. 8056d 05h /
53 Trst active high. Inverted on higher layer. mohor 8056d 05h /
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 8056d 05h /
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 8083d 17h /
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 8083d 17h /
49 This commit was manufactured by cvs2svn to create tag 'sdram_test_working'. 8239d 05h /
48 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8239d 05h /

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