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Rev Log message Author Age Path
69 WBCNTL added, multiple CPU support described. simons 7642d 22h /
68 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7648d 03h /
67 Lower two address lines must be always zero. simons 7648d 03h /
66 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7649d 02h /
65 WB_CNTL register added, some syncronization fixes. simons 7649d 02h /
64 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7669d 03h /
63 Three more chains added for cpu debug access. simons 7669d 03h /
62 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7697d 03h /
61 Lapsus fixed. simons 7697d 03h /
60 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7697d 03h /
59 Reset value for riscsel register set to 1. simons 7697d 03h /
58 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7697d 04h /
57 Multiple cpu support added. simons 7697d 04h /
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7964d 01h /
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7964d 01h /
54 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7964d 02h /
53 Trst active high. Inverted on higher layer. mohor 7964d 02h /
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7964d 02h /
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7991d 14h /
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 7991d 15h /

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