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Rev Log message Author Age Path
74 Removed. mohor 7708d 09h /
73 CRC logic changed. mohor 7708d 09h /
72 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7710d 15h /
71 Mbist support added. simons 7710d 15h /
70 A pdf copy of existing doc document. simons 7717d 17h /
69 WBCNTL added, multiple CPU support described. simons 7738d 07h /
68 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7743d 11h /
67 Lower two address lines must be always zero. simons 7743d 11h /
66 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7744d 11h /
65 WB_CNTL register added, some syncronization fixes. simons 7744d 11h /
64 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7764d 11h /
63 Three more chains added for cpu debug access. simons 7764d 11h /
62 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7792d 11h /
61 Lapsus fixed. simons 7792d 11h /
60 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7792d 12h /
59 Reset value for riscsel register set to 1. simons 7792d 12h /
58 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7792d 13h /
57 Multiple cpu support added. simons 7792d 13h /
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.
mohor 8059d 09h /
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.
mohor 8059d 09h /

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