URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] - Rev 78

Rev	Log message	Author	Age	Path
78	This commit was manufactured by cvs2svn to create tag 'old_debug'.		7708d 06h	/
77	MBIST chain connection fixed.	mohor	7708d 06h	/
76	This commit was manufactured by cvs2svn to create tag 'rel_10'.		7708d 07h	/
75	Simulation files.	mohor	7708d 07h	/
74	Removed.	mohor	7708d 07h	/
73	CRC logic changed.	mohor	7708d 08h	/
72	This commit was manufactured by cvs2svn to create tag 'rel_9'.		7710d 14h	/
71	Mbist support added.	simons	7710d 14h	/
70	A pdf copy of existing doc document.	simons	7717d 16h	/
69	WBCNTL added, multiple CPU support described.	simons	7738d 05h	/
68	This commit was manufactured by cvs2svn to create tag 'rel_8'.		7743d 10h	/
67	Lower two address lines must be always zero.	simons	7743d 10h	/
66	This commit was manufactured by cvs2svn to create tag 'rel_7'.		7744d 09h	/
65	WB_CNTL register added, some syncronization fixes.	simons	7744d 09h	/
64	This commit was manufactured by cvs2svn to create tag 'rel_6'.		7764d 10h	/
63	Three more chains added for cpu debug access.	simons	7764d 10h	/
62	This commit was manufactured by cvs2svn to create tag 'rel_5'.		7792d 10h	/
61	Lapsus fixed.	simons	7792d 10h	/
60	This commit was manufactured by cvs2svn to create tag 'rel_4'.		7792d 10h	/
59	Reset value for riscsel register set to 1.	simons	7792d 10h	/