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7 Two sources belonging to the last commit, whose comments go with the
last commit, that just didn't make it in time.		 dgisselq 3561d 17h /
6 Lots of work accomplished today. Test benches now exist and work for the:
butterfly, multiply, bitreversal, pairwise FFT stage (dblstage), and the
four-wise FFT stage (qtrstage). Work continues on the single (generic)
FFT stage, and (of course) the FFT isn't ready yet. A second commit will
follow this one shortly with the new files added (oops!--I should've added
them this time--my bad.)		 dgisselq 3561d 17h /
5 The butterfly_tb is now written, and the butterfly succeeds at the test
bench!		 dgisselq 3562d 00h /
4 Bench tests updated, they now state SUCCESS upon successful completion,
return a 0 on success, and all bench tests test all function outputs
(now).		 dgisselq 3562d 05h /
3 The first upload of the s/w didn't take. Had it taken, the comment would've
been: This is the first upload of the double clocked FFT software. While it
should (roughly) be complete, a lot of work remains to be done--primarily
in building test benches, modifying the interface of fftgen to make it
more friendly, etc. In fact, the c++ code not only compiles, but the
Verilog code it produces actually builds as well!

Now, however, I have several test benches written, and have verified the
unit functionality of the multiply, bit reversal stage, the dblstage (FFT
len 2), and the qtrstage (FFT len 4). I then took a closer look at the
multiply, discovered it failed at signed integers and rebuilt it. The
new test bench tests the full 16-bit signed integer support properly. This
leaves butterflies and generic FFT stages that still need test benches, as
does the main (I)FFT program.		 dgisselq 3562d 05h /
2 Here's an attempt at a first subversion update. dgisselq 3562d 06h /
1 The project and the structure was created root 3567d 00h /

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