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Rev Log message Author Age Path
308 multicycle design, suitable for being verilated hellwig 3394d 06h /
307 several tests got duration.dat files hellwig 3394d 20h /
306 tool to show display output added hellwig 3395d 03h /
305 tool to show serial output added hellwig 3395d 04h /
304 Makefile updated hellwig 3397d 14h /
303 multicycle simulation control files added hellwig 3397d 14h /
302 tests updated hellwig 3397d 19h /
301 multicycle simulation source files added hellwig 3398d 03h /
300 memdelay experiment code looking better now hellwig 3398d 03h /
299 s3e-500 dac simulation corrected hellwig 3398d 04h /
298 xsa-xst-3 dac simulation corrected hellwig 3398d 05h /
297 memdelay experiment added hellwig 3398d 06h /
296 memspeed experiment added hellwig 3398d 18h /
295 tests for FPGA implementations hellwig 3399d 05h /
294 avoid ptrdiff_t warning in cpp, again hellwig 3400d 15h /
293 avoid ptrdiff_t warning in cpp hellwig 3400d 15h /
292 directory structure for FPGA implementations and simulations hellwig 3400d 20h /
291 avoid timing violations in DDR RAM circuit, new .bit files generated hellwig 3400d 21h /
290 Wishbone-compatible bus signals hellwig 3402d 21h /
289 new directory structure within fpga hellwig 3403d 18h /

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