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Rev Log message Author Age Path
77 hardware: ucf file re-formatted hellwig 4019d 12h /
76 AUTHORS update hellwig 4020d 03h /
75 hardware: cpu now equal to port-15 hellwig 4020d 04h /
74 when simulating the system include a console hellwig 4020d 08h /
73 use xess monitor when simulating the system hellwig 4020d 09h /
72 simulator: IRQ 0-3 explanation changed hellwig 4020d 12h /
71 simulator: IRQ 15 explanation added hellwig 4020d 12h /
70 hardware: two timers hellwig 4021d 04h /
69 hardware: timer counts clock cycles, counter is readable hellwig 4021d 07h /
68 hardware: timer now equal to port-15 hellwig 4021d 11h /
67 fpga implementation update hellwig 4021d 13h /
66 bin2exo: no S0 header any longer hellwig 4022d 07h /
65 xess monitor update hellwig 4022d 09h /
64 monitors re-organized hellwig 4022d 11h /
63 monitors re-organized hellwig 4022d 12h /
62 monitors re-organized hellwig 4022d 12h /
61 monitors re-organized hellwig 4022d 12h /
60 monitors re-organized hellwig 4022d 13h /
59 monitors re-organized hellwig 4022d 13h /
58 monitors re-organized hellwig 4022d 13h /

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