URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 368

Rev	Log message	Author	Age	Path
368	dbg_dat0 only exist when `DEBUG_WISHBONE is set	olof	4667d 13h	/
367	Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored	olof	4730d 10h	/
366	Readded eth_top.v with a deprecation warning	olof	4854d 14h	/
365	Whitespace cleanup	olof	4855d 13h	/
364	Renamed eth_top.v to ethmac.v to fit better into OpenCores structure	olof	4856d 11h	/
363	quartus project files	unneback	4856d 19h	/
362	added Makefiles to build project	unneback	4856d 20h	/
361	created branch unneback	unneback	4856d 20h	/
360	Added partial implementation of the debug register from ORPSoC	olof	4857d 18h	/
359	Verilator linting fixes	olof	4859d 20h	/
358	Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version	olof	4861d 10h	/
357	Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC	olof	4861d 11h	/
356	Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure	olof	4861d 12h	/
355	Import Julius Baxter's verilator hints from ORPSoC	olof	4861d 13h	/
354	Whitespace cleanup	olof	4861d 14h	/
353	Inherit fixes for bit width of constants from ORPSoC	olof	4863d 15h	/
352	Removed delayed assignments from rtl code	olof	4867d 21h	/
351	Turn defines into parameters in eth_cop	olof	4876d 11h	/
350	Turn M[1-2]_ADDRESSED_S[1-2] defines into wires	olof	4876d 11h	/
349	Make all parameters configurable from top level	olof	4877d 12h	/