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Rev	Log message	Author	Age	Path
108	Testbench supports unaligned accesses.	mohor	8273d 07h	/
107	TX_BUF_BASE changed.	mohor	8273d 07h	/
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8273d 07h	/
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8282d 09h	/
104	FCS should not be included in NibbleMinFl.	mohor	8284d 03h	/
103	Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v	mohor	8284d 03h	/
102	Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled or not.	mohor	8284d 03h	/
101	Short frame and ReceivedLengthOK were not detected correctly.	mohor	8284d 04h	/
100	Generic ram or Xilinx ram can be used in fifo (selectable by setting ETH_FIFO_XILINX in eth_defines.v).	mohor	8284d 04h	/
99	Document revised.	mohor	8291d 02h	/
98	Document revised.	mohor	8291d 03h	/
97	Small typo fixed.	lampret	8308d 01h	/
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8312d 01h	/
95	md_padoen_o changed to md_padoe_o. Signal was always active high, just name was incorrect.	mohor	8312d 04h	/
94	When clear and read/write are active at the same time, cnt and pointers are set to 1.	mohor	8312d 04h	/
93	When in promiscous mode some frames were not received correctly. Fixed.	mohor	8317d 02h	/
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8318d 05h	/
91	Comments in Slovene language removed.	mohor	8318d 05h	/
90	casex changed with case, fifo reset changed.	mohor	8318d 05h	/
89	TX_BD_NUM, MAC_ADDR0 and MAC_ADDR1 register description changed.	mohor	8322d 03h	/

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[/] - Rev 108

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