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166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 8092d 11h /
165 HASH improvement needed. mohor 8092d 14h /
164 Ethernet debug registers removed. mohor 8092d 14h /
163 Another temporary version. Core is almost finished. Testbench not included,
yet"		 mohor 8093d 06h /
162 Another temporary version. Core is almost finished. Testbench not included,
yet.		 mohor 8093d 06h /
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 8093d 11h /
160 error acknowledge cycle termination added to display. mohor 8093d 12h /
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 8094d 08h /
158 Typo fixed. mohor 8094d 08h /
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 8096d 13h /
156 Valid testbench. mohor 8096d 13h /
155 Minor changes. mohor 8096d 13h /
154 Design document is still under construction. mohor 8097d 13h /
153 Temp version (backup). mohor 8098d 04h /
152 Version 1.16 created. See revision history in the document for details. mohor 8098d 04h /
151 This commit was manufactured by cvs2svn to create tag 'rel_4'. 8098d 06h /
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.		 mohor 8098d 06h /
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.		 mohor 8098d 06h /
148 Bug when last byte of destination address was not checked fixed. mohor 8098d 06h /
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.		 mohor 8098d 06h /

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