URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 219

Rev	Log message	Author	Age	Path
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	8085d 02h	/
218	Typo error fixed. (When using Bist)	mohor	8085d 04h	/
217	Bist supported.	mohor	8085d 04h	/
216	Bist signals added.	mohor	8085d 04h	/
215	Bist supported.	mohor	8085d 05h	/
214	Signals for WISHBONE B3 compliant interface added.	mohor	8086d 01h	/
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	8086d 01h	/
212	Minor $display change.	mohor	8086d 01h	/
211	Bist added.	mohor	8086d 01h	/
210	BIST added.	mohor	8086d 01h	/
209	Just back-up; not completed testbench and some testcases are not wotking properly yet.	tadejm	8087d 04h	/
208	Virtual Silicon RAMs moved to lib directory	tadej	8102d 22h	/
207	Virtual Silicon RAM support fixed	tadej	8102d 23h	/
206	Virtual Silicon RAM added to the simulation.	mohor	8102d 23h	/
205	ETH_VIRTUAL_SILICON_RAM supported.	mohor	8102d 23h	/
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	8102d 23h	/
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	8102d 23h	/
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	8106d 01h	/
201	Core size added to the document.	mohor	8106d 01h	/
200	File with lower case checked in instead.	mohor	8106d 01h	/