URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 221

Rev	Log message	Author	Age	Path
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	8078d 08h	/
220	This commit was manufactured by cvs2svn to create tag 'rel_5'.		8081d 08h	/
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	8081d 08h	/
218	Typo error fixed. (When using Bist)	mohor	8081d 10h	/
217	Bist supported.	mohor	8081d 10h	/
216	Bist signals added.	mohor	8081d 10h	/
215	Bist supported.	mohor	8081d 11h	/
214	Signals for WISHBONE B3 compliant interface added.	mohor	8082d 07h	/
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	8082d 07h	/
212	Minor $display change.	mohor	8082d 07h	/
211	Bist added.	mohor	8082d 07h	/
210	BIST added.	mohor	8082d 07h	/
209	Just back-up; not completed testbench and some testcases are not wotking properly yet.	tadejm	8083d 11h	/
208	Virtual Silicon RAMs moved to lib directory	tadej	8099d 04h	/
207	Virtual Silicon RAM support fixed	tadej	8099d 05h	/
206	Virtual Silicon RAM added to the simulation.	mohor	8099d 05h	/
205	ETH_VIRTUAL_SILICON_RAM supported.	mohor	8099d 05h	/
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	8099d 05h	/
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	8099d 05h	/
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	8102d 07h	/