URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 224

Rev	Log message	Author	Age	Path
224	Signals for a wave window in Modelsim.	tadejm	8105d 02h	/
223	Some code changed due to bug fixes.	tadejm	8105d 02h	/
222	This commit was manufactured by cvs2svn to create tag 'rel_6'.		8109d 00h	/
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	8109d 00h	/
220	This commit was manufactured by cvs2svn to create tag 'rel_5'.		8112d 01h	/
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	8112d 01h	/
218	Typo error fixed. (When using Bist)	mohor	8112d 03h	/
217	Bist supported.	mohor	8112d 03h	/
216	Bist signals added.	mohor	8112d 03h	/
215	Bist supported.	mohor	8112d 03h	/
214	Signals for WISHBONE B3 compliant interface added.	mohor	8112d 23h	/
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	8112d 23h	/
212	Minor $display change.	mohor	8112d 23h	/
211	Bist added.	mohor	8113d 00h	/
210	BIST added.	mohor	8113d 00h	/
209	Just back-up; not completed testbench and some testcases are not wotking properly yet.	tadejm	8114d 03h	/
208	Virtual Silicon RAMs moved to lib directory	tadej	8129d 21h	/
207	Virtual Silicon RAM support fixed	tadej	8129d 21h	/
206	Virtual Silicon RAM added to the simulation.	mohor	8129d 21h	/
205	ETH_VIRTUAL_SILICON_RAM supported.	mohor	8129d 22h	/