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Rev	Log message	Author	Age	Path
247	This commit was manufactured by cvs2svn to create tag 'rel_10'.		8050d 00h	/
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	8050d 00h	/
245	Rev 1.7.	mohor	8050d 18h	/
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	8050d 20h	/
243	Late collision is not reported any more.	tadejm	8051d 01h	/
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	8051d 16h	/
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	8051d 16h	/
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	8051d 16h	/
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	8051d 16h	/
238	Defines fixed to use generic RAM by default.	mohor	8063d 20h	/
237	This commit was manufactured by cvs2svn to create tag 'rel_9'.		8066d 02h	/
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	8066d 02h	/
235	rev 4.	mohor	8066d 16h	/
234	Figure list assed to the revision 3.	mohor	8067d 00h	/
233	Revision 0.3 released. Some figures added.	mohor	8067d 01h	/
232	fpga define added.	mohor	8071d 20h	/
231	Description of Core Modules added (figure).	mohor	8073d 21h	/
230	This commit was manufactured by cvs2svn to create tag 'rel_8'.		8077d 18h	/
229	case changed to casex.	mohor	8077d 18h	/
228	This commit was manufactured by cvs2svn to create tag 'rel_7'.		8077d 21h	/

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