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Rev	Log message	Author	Age	Path
248	wb_rst_i is used for MIIM reset.	mohor	8421d 22h	/
247	This commit was manufactured by cvs2svn to create tag 'rel_10'.		8425d 01h	/
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	8425d 01h	/
245	Rev 1.7.	mohor	8425d 19h	/
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	8425d 21h	/
243	Late collision is not reported any more.	tadejm	8426d 02h	/
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	8426d 17h	/
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	8426d 17h	/
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	8426d 17h	/
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	8426d 17h	/
238	Defines fixed to use generic RAM by default.	mohor	8438d 21h	/
237	This commit was manufactured by cvs2svn to create tag 'rel_9'.		8441d 02h	/
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	8441d 02h	/
235	rev 4.	mohor	8441d 17h	/
234	Figure list assed to the revision 3.	mohor	8442d 01h	/
233	Revision 0.3 released. Some figures added.	mohor	8442d 01h	/
232	fpga define added.	mohor	8446d 20h	/
231	Description of Core Modules added (figure).	mohor	8448d 22h	/
230	This commit was manufactured by cvs2svn to create tag 'rel_8'.		8452d 18h	/
229	case changed to casex.	mohor	8452d 18h	/

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[/] - Rev 248

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