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Rev Log message Author Age Path
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 8039d 22h /
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 8040d 10h /
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).
mohor 8040d 23h /
258 This commit was manufactured by cvs2svn to create tag 'rel_12'. 8041d 00h /
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
mohor 8041d 00h /
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.
mohor 8041d 00h /
255 TPauseRq synchronized to tx_clk. mohor 8041d 00h /
254 Temp version. mohor 8042d 03h /
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 8042d 06h /
252 Just some updates. tadejm 8042d 06h /
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 8042d 06h /
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 8042d 06h /
249 This commit was manufactured by cvs2svn to create tag 'rel_11'. 8043d 06h /
248 wb_rst_i is used for MIIM reset. mohor 8043d 06h /
247 This commit was manufactured by cvs2svn to create tag 'rel_10'. 8046d 09h /
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 8046d 09h /
245 Rev 1.7. mohor 8047d 03h /
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 8047d 05h /
243 Late collision is not reported any more. tadejm 8047d 11h /
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 8048d 01h /

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