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Rev	Log message	Author	Age	Path
263	test_mac_full_duplex_flow_control tests pretty much finished. TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps ) finished. TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps ) finished.	mohor	8074d 16h	/
262	Version 1.18 released. MIIMRST (Reset of the MIIM module) not used any more in the MIIMODER register. Control Frame bit (CF) added to the RX buffer descriptor. Control frame detection section updated.	mohor	8074d 16h	/
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	8074d 16h	/
260	test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame finished.	mohor	8075d 04h	/
259	In loopback rx_clk is not looped back. Possible CRC error. Consider if usage of additional logic is necessery (FIFO for looping the data).	mohor	8075d 18h	/
258	This commit was manufactured by cvs2svn to create tag 'rel_12'.		8075d 18h	/
257	When TxUsedData and CtrlMux occur at the same time, byte counter needs to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.	mohor	8075d 18h	/
256	TxDone and TxAbort changed so they're not propagated to the wishbone module when control frame is transmitted.	mohor	8075d 18h	/
255	TPauseRq synchronized to tx_clk.	mohor	8075d 18h	/
254	Temp version.	mohor	8076d 22h	/
253	r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.	mohor	8077d 00h	/
252	Just some updates.	tadejm	8077d 01h	/
251	When control frame (PAUSE) was sent, status was written in the eth_wishbone module and both TXB and TXC interrupts were set. Fixed. Only TXC interrupt is set.	mohor	8077d 01h	/
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	8077d 01h	/
249	This commit was manufactured by cvs2svn to create tag 'rel_11'.		8078d 01h	/
248	wb_rst_i is used for MIIM reset.	mohor	8078d 01h	/
247	This commit was manufactured by cvs2svn to create tag 'rel_10'.		8081d 04h	/
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	8081d 04h	/
245	Rev 1.7.	mohor	8081d 22h	/
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	8082d 00h	/

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[/] - Rev 263

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