URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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[/] - Rev 313

Rev	Log message	Author	Age	Path
313	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7826d 03h	/
312	Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.	tadejm	7826d 03h	/
311	Update script for running different file list files for different RAM models.	tadejm	7826d 03h	/
310	More signals.	tadejm	7826d 03h	/
309	Update file list files for different RAM models with byte select accessing.	tadejm	7826d 03h	/
308	Moved RAM model file path from sim_file_list.lst to this file.	tadejm	7826d 03h	/
307	This commit was manufactured by cvs2svn to create tag 'rel_24'.		7827d 01h	/
306	Lapsus fixed (!we -> ~we).	simons	7827d 01h	/
305	This commit was manufactured by cvs2svn to create tag 'rel_23'.		7848d 21h	/
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7848d 21h	/
303	This commit was manufactured by cvs2svn to create tag 'rel_22'.		7875d 08h	/
302	mbist signals updated according to newest convention	markom	7875d 08h	/
301	Update RxEnSync only when mrxdv_pad_i is inactive (LOW).	knguyen	7886d 00h	/
300	This commit was manufactured by cvs2svn to create tag 'rel_21'.		7933d 03h	/
299	Artisan RAMs added.	mohor	7933d 03h	/
298	This commit was manufactured by cvs2svn to create tag 'rel_20'.		7938d 23h	/
297	Artisan ram instance added.	simons	7938d 23h	/
296	This commit was manufactured by cvs2svn to create tag 'rel_19'.		7940d 02h	/
295	Few minor changes.	tadejm	7940d 02h	/
294	Added path to a file with distributed RAM instances for xilinx.	tadejm	7942d 02h	/