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Rev Log message Author Age Path
327 Defer indication fixed. igorm 7248d 05h /
326 Delayed CRC fixed. igorm 7248d 05h /
325 Defer indication fixed. igorm 7248d 05h /
324 This commit was manufactured by cvs2svn to create tag 'rel_27'. 7545d 06h /
323 Accidently deleted line put back. igorm 7545d 06h /
322 This commit was manufactured by cvs2svn to create tag 'rel_26'. 7549d 01h /
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries		 igorm 7549d 01h /
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 7549d 04h /
319 Latest Ethernet IP core testbench. tadejm 7580d 00h /
318 Latest Ethernet IP core testbench. tadejm 7580d 00h /
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 7589d 07h /
316 This commit was manufactured by cvs2svn to create tag 'rel_25'. 7692d 03h /
315 Updated testbench. Some more testcases, some repaired. tadejm 7692d 03h /
314 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7692d 03h /
313 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7692d 03h /
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7692d 03h /
311 Update script for running different file list files for different RAM models. tadejm 7692d 03h /
310 More signals. tadejm 7692d 03h /
309 Update file list files for different RAM models with byte select accessing. tadejm 7692d 03h /
308 Moved RAM model file path from sim_file_list.lst to this file. tadejm 7692d 03h /

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