URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 34

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8417d 13h	/
33	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8417d 17h	/
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8417d 17h	/
31	RX_BD_NUM register added instead of the RB_BD_ADDR.	mohor	8417d 18h	/
30	BD section updated.	mohor	8419d 15h	/
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8439d 13h	/
28	New release. Name changed to lower case.	mohor	8442d 05h	/
27	File names changed to lower case.	mohor	8442d 05h	/
26	First release of product brief.	mohor	8442d 05h	/
25	First release of product brief.	mohor	8442d 05h	/
24	Log file added.	mohor	8464d 16h	/
23	Number of addresses (wb_adr_i) minimized.	mohor	8464d 16h	/
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8464d 19h	/
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8465d 16h	/
20	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8489d 13h	/
19	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8489d 13h	/
18	Few little NCSIM warnings fixed.	mohor	8502d 14h	/
17	Signal names changed on the top level for easier pad insertion (ASIC).	mohor	8529d 14h	/
16	"else" was missing within the always block in file eth_wishbonedma.v.	mohor	8536d 19h	/
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8538d 13h	/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories ethmac

[/] - Rev 34

Filtering Options