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Rev Log message Author Age Path
351 Turn defines into parameters in eth_cop olof 4817d 02h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4817d 03h /
349 Make all parameters configurable from top level olof 4818d 04h /
348 Added option to dump VCD files olof 4819d 03h /
347 Added information about running with Icarus Verilog olof 4819d 03h /
346 Updated project location olof 4819d 05h /
345 Temporarily disable failing tests olof 4819d 07h /
344 bit 9 in phy control register is self clearing olof 4825d 09h /
343 Address miss should not be asserted on short frames olof 4829d 05h /
342 Added cast to avoid inequality when comparing different data types olof 4829d 05h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4829d 05h /
340 Don't fail if log dir already exists olof 4830d 03h /
339 Added basic support for Icarus Verilog olof 4831d 02h /
338 root 5623d 08h /
337 root 5679d 10h /
336 Added old uploaded documents to new repository. root 5680d 13h /
335 New directory structure. root 5680d 13h /
334 Minor fixes for Icarus simulator. igorm 7128d 15h /
333 Some small fixes + some troubles fixed. igorm 7129d 03h /
332 Case statement improved for synthesys. igorm 7142d 08h /

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