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40 This commit was manufactured by cvs2svn to create tag 'V10'. 6728d 17h /
39 first version fisher5090 6728d 17h /
38 deleted fisher5090 6728d 18h /
37 no message fisher5090 6728d 18h /
36 no message godzilla 6792d 02h /
35 no message godzilla 6795d 02h /
34 Rewritten code. godzilla 6795d 02h /
33 Rewritten code. godzilla 6795d 02h /
32 no message fisher5090 6812d 10h /
31 no message fisher5090 6812d 10h /
30 no message fisher5090 6840d 09h /
29 no message fisher5090 6840d 19h /
28 First commit. 32-bit counter. Synthesizes with no errors in Xilinx XST. mvpratt 6843d 05h /
27 xilinx coregen fisher5090 6853d 10h /
26 good edition fisher5090 6853d 10h /
25 no message fisher5090 6853d 10h /
24 First cut. One of the main culprits for the timing violations. godzilla 6856d 01h /
23 First cut. Original code from Easic but add some extra controls. One of the main culprits for the timing violations. godzilla 6856d 01h /
22 First cut. Original code from Easic but add some extra controls. godzilla 6856d 01h /
21 First cut. Not thoroughly tested yet but still need to implement the configuration, non-crc version and stats.
So far Leonardo Precison indicates the design can run upto 101 MHz but need to remove the timing violations to increase speed.
godzilla 6856d 01h /

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