| Rev |
Log message |
Author |
Age |
Path |
| 27 |
some of the problems are fixed now, some still remain.
all transfersize counter where wrong. they have to count the correct number of bytes transfered.
handling of a "short word" added, to be shure that all data (also when it is shorter than a word)
is transfered.
corrected some errors with the fifo write enable signals. |
nussgipfel |
5420d 17h |
/ |
| 26 |
basic in/out transfers working. tester consumes data and generates the test messages.
protocol handling is working. at the moment it gets out of sync for long data outs.
for in transfers, to less data is sent to the host, deadlock for long in transfers. |
nussgipfel |
5424d 06h |
/ |
| 25 |
small update in the comments |
nussgipfel |
5429d 13h |
/ |
| 24 |
first version of the GECKO3COM_simple_test that successfully synthesized.
debugging starts now.
fixed a small bug in the gpif_com_test due to the adding of the gpif_com_eom signal and the eom bit
flip-flop in the gpif_com module. |
nussgipfel |
5429d 13h |
/ |
| 23 |
GECKO3COM_simple_test designed and written.
added needed switches to the ucf files.
did some cleanup in the GECKO3_simple_* |
nussgipfel |
5431d 09h |
/ |
| 22 |
a lot of work is done for the GECKO3COM_simple IP core. datapath and fsm is designed and implemente,
top level is implemented. needs still some tweks but time to make a backup!
the simple ip core will be tested together with the GECKO3COM_simple_test. |
nussgipfel |
5432d 17h |
/ |
| 21 |
system is fully working and tested with big files over 4 Gbyte. there were some smaller bugs and glitches which caused
sometimes a deadlock. they are fixed now.
one was because the fx2 reads the done pin sometimes wrong during a long data
transfer. I don't now if this is because of crosstalk on my prototyping system or fpga internal weakness.
a simple debouncing (read again after 40 ms) did the trick.
changed firmware version to 0.5rc0, basically all features targeted for 0.5 are done. |
nussgipfel |
5447d 12h |
/ |
| 20 |
basic synchronous IN (fpga to host) transfer works.
detail changes:
-the scpi command "fpga:data" checks now, if the fpga is configured before it changes the context to the fpga. if the fpga is
not configured, it returns an "EXECUTE ERROR".
in the same way, the main_loop checks if the fpga looses his configuration. it disables the GPIF, switches the context back
to the fx2 if so. this is mainly to avoid undeterministic behaviour if you reconfigure the fpga via jtag.
-introduced the new signal "EOM" end of message from the "usb tmc protokoll interpreter" to the gpif_com module
-changed the GPIF waveform for the FIFO IN transfer to the new scheme.
-implemented the same waveform into the gpif_com_fsm.vhd. works well together.
-bugfixed the gpif_com_test.vhd. sends the new EOM signal, the response message generator works now as it should.
-added the missing AUTHORS README and COPYING (license) files to the core directory. |
nussgipfel |
5448d 10h |
/ |
| 19 |
found a pinning error in the series production documentation. fixed in the wiki and the core.
really stable host to fpga data transfer achieved. several time over 4Gbyte transfered. including switching to fpga to
host GPIF waveform to listen to possible fpga transfer tries. but fpga to host transfers still not finished.
the correct length of data is read from the gpif_fsm now. still untested data consitency when data flow throtling occours.
need bigger buffers to test this. will be done on a higher level. |
nussgipfel |
5456d 12h |
/ |
| 18 |
I achieved now stable OUT transfers (from the PC to the FPGA) with working throtling (when the FPGA consumes data slower than the host delivers).
The basics needed for this are implemented in the FPGA like handshaking with the FX2 and clock domain transistion from the Interface clock to the user defined system clock.
in the gpif_com_test.vhd is a message rom, containing a prepared answer message to generate an IN transfer. this is needed for the next step. |
nussgipfel |
5459d 20h |
/ |
| 17 |
killed a bug that caused unreliable out transfers. detection of a ongoing in transfer is malfunctioning. needs redesign. |
nussgipfel |
5461d 10h |
/ |
| 16 |
release candidate 3: 0.4rc3
fixed a bug in the get_capabilities function. was fixed before but it was back again...
removed one file from the build process, that shouldn't be in the subversion. |
nussgipfel |
5474d 16h |
/ |
| 15 |
this is the release of version 0.4rc2
we provide now the downloadable *.iic file of the current version in the repository at the convinient place
"gecko3com-fw/firmware/" |
nussgipfel |
5487d 17h |
/ |
| 14 |
reorganising and renaming the stuff in these project.
the core will get the name "GECKO3COM_" followed by the type "simple", "plb" or "opb"
to follow the naming in the GECKO3 wiki and to show the IP core interface.
duplicated fifo corecenerator files are merged together including a wrapper to easily supress synthesizer warnings
from unavailable, unused and unconnected pins.
the project is now organised in a way how the IP core and it's parts are beeing used. this means that the
low-level gpif access module is instantiated by the higher level modules and not the other way around.
this will make more sense when more parts of this IP core are finished (planning is finished, they have
to be implemented and tested now). |
nussgipfel |
5487d 17h |
/ |
| 13 |
included the gecko3com_0.31.tar.gz firmware package needed to initialize fresh produced boards without any
serial number or fpga type information.
fixed two bugs that were found during testing of the version 0.4-rc
- the GET_CAPABILITIES function in the usb_tmc module was using a wrong pointer and returned garbage
- the SLOT_ADRESS defines for the spi write functions were using constants only usable on the GECKO3main prototype
changed some other small stuff to avoid compiler warnings or clarifie some comments. |
nussgipfel |
5487d 19h |
/ |
| 12 |
this is the version 0.4 of the GECKO3com IP core.
This is the last version from Andreas Habegger, the maintainer for this core is now Christoph Zimmermann |
nussgipfel |
5502d 20h |
/ |
| 11 |
initial add of the version 0.3 of the GECKO3com IP core. originaly developped by Andreas Habegger.
this commit is just for backup and to make the project progress visible because version 0.4 is also ready and will be commited in the next step. |
nussgipfel |
5502d 20h |
/ |
| 10 |
this import did go wrong. look at GECKO3COM/ |
nussgipfel |
5519d 17h |
/ |
| 9 |
First commit to the OC svn.
This is the release candidate for the GECKO3COM firmware version 0.4.
Included are all sources, scripts and helper tools.
Implemented functionality to this firmware version:
- FW upgrade through USB DFU class
- works as a USB TMC device (test and measurement class)
- handles all mandatory IEEE488 and SCPI commands
- fpga can be configured through USB
- two different fpga configuration files can be downloaded the the onboard memory
- loads one of these configuration files during power on
next step is to implement the transparent data communication between the USB host and the FPGA |
nussgipfel |
5519d 17h |
/ |
| 8 |
First commit to the OC svn.
This is the release candidate for the GECKO3COM firmware version 0.4.
Included are all sources, scripts and helper tools.
Implemented functionality to this firmware version:
- FW upgrade through USB DFU class
- works as a USB TMC device (test and measurement class)
- handles all mandatory IEEE488 and SCPI commands
- fpga can be configured through USB
- two different fpga configuration files can be downloaded the the onboard memory
- loads one of these configuration files during power on
next step is to implement the transparent data communication between the USB host and the FPGA |
nussgipfel |
5519d 17h |
/ |
