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47 Added test case of -16 negative period_adj value, to show the effect trying to set time backwards. Thanks to Frank Yang's question. edn_walter 4611d 19h /
46 Added operation details to the memory map doc. Memory map should be interpreted with help of ptp_drv_bfm.c. edn_walter 4614d 11h /
45 1. optimized area, by removing unused registers.
2. optimized timing, by removing latches.		 edn_walter 4615d 02h /
44 Updated TSU testbench. edn_walter 4615d 04h /
43 Added software configurable PTP message id mask for TSU parser. edn_walter 4616d 02h /
42 Updated RTC testbench. Shrunk 1s to 1us to simulate more cycles during a short time. edn_walter 4616d 08h /
41 Added pre-adder to the accumulator to cut down critical timing path. edn_walter 4616d 10h /
40 Release version 1.1 edn_walter 4616d 13h /
39 1. Added memory map and feature description.
2. Separated TX RX TSU register addresses.		 edn_walter 4616d 13h /
38 1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.		 edn_walter 4617d 11h /
37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4617d 14h /
36 TSU testbench is now self-checking. Test result is reported at end of simulation. edn_walter 4618d 09h /
35 Added support for stacked MPLS UDP/IPv4/IPv6 PTP packets. edn_walter 4619d 08h /
34 Added LGPL file header to all copyrighted files. edn_walter 4619d 11h /
33 Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules. edn_walter 4619d 12h /
32 Added PTP standard time format output to the top module. Can be connected to external modules. edn_walter 4619d 15h /
31 Added hand-shaking for the TSU data reading. edn_walter 4620d 08h /
30 Timestamp format in the queue = msgId_4bit + seqId_16bit + null_8bit + timeStamp1s_4bit + null_2bit + timeStamp1ns_30bit edn_walter 4620d 08h /
29 Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz. edn_walter 4620d 08h /
28 Before changing TSU packet parser datapath width from 32b to 8b. edn_walter 4620d 15h /

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