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Rev Log message Author Age Path
76 Prepare for adding new system integration tool support. ash_riple 2580d 07h /
75 Added empty folder sys/xilinx_ipi. ash_riple 2580d 07h /
74 Changed the name of system integration folders, going to add xilinx IPI support for Vivado. ash_riple 2580d 07h /
73 Corrected AXI4 wrapper timing bug.
Added system-level instantiation examples for XPS and Qsys.		 ash_riple 3826d 10h /
72 Minor changes. ash_riple 4152d 07h /
71 Added architecture description in the doc folder. ash_riple 4152d 08h /
70 Updated Altera Qsys instantiation script. ash_riple 4308d 05h /
69 Fixed the negative period adjustment bug. ash_riple 4309d 10h /
68 Refined the vendor specific IP instanttiation. Now DCFIFO is instantiated as a vendor specific IP in PAR directory. ash_riple 4309d 14h /
67 Updated the WishBone IP top and Qsys IP top. ash_riple 4311d 07h /
66 Added IP instantiation support for: QSys, XPS and WishBone. ash_riple 4312d 06h /
65 Added WishBone compatible wrapper for register access. ash_riple 4316d 11h /
64 Added PTPv2 timing analyzer tool. ash_riple 4318d 07h /
63 Updated the simulation script under Linux. ash_riple 4321d 12h /
62 Removed environment variable settings in the simulation script under Windows. ash_riple 4321d 12h /
61 Made different scripts for top-level simulation to run under Linux. ash_riple 4321d 13h /
60 Made different scripts for top-level simulation to run under Linux. ash_riple 4321d 13h /
59 Made different scripts for top-level simulation to run under Windows. ash_riple 4321d 13h /
58 Added output rtc_time_one_pps for clock accuracy measurement. 1PPS output is leading edge aligned with the PTP time output on boundary of 1s. edn_walter 4594d 10h /
57 Added parameters of frame header constants for packet parsing. edn_walter 4594d 11h /

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