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6 High-speed version with comparator moved from a function to the
separate VHDL component (with 1 clock period latency).
It allows better utilization of the platform-specific features.
wzab 2429d 09h /
5 Added new high-speed version capable to work at higher speed, but using 4
clk cycles per data word.
wzab 2429d 23h /
4 Added file implementing dual port common clock RAM inferrable in synthesis. wzab 4141d 20h /
3 Eliminated synthesis of latches for a few signals wzab 4141d 21h /
2 Initial commit of version previously hosted at http://www.ise.pw.edu.pl/~wzab/fpga_heapsort wzab 4403d 04h /
1 The project and the structure was created root 4404d 21h /

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