OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] - Rev 14

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 8423d 18h /
13 Fixed some synthesis warnings. rherveille 8434d 22h /
12 no message rherveille 8440d 14h /
11 Changed RST_LVL define to parameter. rherveille 8443d 21h /
10 Created new directory structure.
Added Verilog version.
rherveille 8465d 18h /
9 Created directory structure (documentation, vhdl, verilog) rherveille 8535d 13h /
8 Created directory structure (documentation, vhdl, verilog) rherveille 8535d 13h /
7 added some remarks, fixed some sensitivity lists rherveille 8604d 16h /
6 fixed typo txt -> txr rherveille 8608d 19h /
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8615d 17h /
4 WISHBONE I2C Master Core: initial release rherveille 8667d 21h /
3 This commit was manufactured by cvs2svn to create tag 'first'. 8729d 20h /
2 initial release rherveille 8729d 20h /
1 Standard project directories initialized by cvs2svn. 8729d 20h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.