URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] - Rev 15

Rev	Log message	Author	Age	Path
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8472d 00h	/
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8472d 00h	/
13	Fixed some synthesis warnings.	rherveille	8483d 04h	/
12	no message	rherveille	8488d 19h	/
11	Changed RST_LVL define to parameter.	rherveille	8492d 03h	/
10	Created new directory structure. Added Verilog version.	rherveille	8513d 23h	/
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8583d 18h	/
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8583d 18h	/
7	added some remarks, fixed some sensitivity lists	rherveille	8652d 21h	/
6	fixed typo txt -> txr	rherveille	8657d 01h	/
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8663d 23h	/
4	WISHBONE I2C Master Core: initial release	rherveille	8716d 02h	/
3	This commit was manufactured by cvs2svn to create tag 'first'.		8778d 01h	/
2	initial release	rherveille	8778d 01h	/
1	Standard project directories initialized by cvs2svn.		8778d 01h	/