URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] - Rev 34

Rev	Log message	Author	Age	Path
34	Fixed a few 'arbitration lost' bugs. VHDL version only.	rherveille	8034d 00h	/
33	Fixed a bug in the Command Register declaration.	rherveille	8056d 09h	/
32	Multi-master capabilities added to the core. Changed documentation accordingly. Updated some timing diagrams.	rherveille	8066d 08h	/
31	Core is now a Multimaster I2C controller.	rherveille	8070d 10h	/
30	Small code simplifications	rherveille	8070d 10h	/
29	Core is now a Multimaster I2C controller	rherveille	8070d 11h	/
28	* empty log message *	rherveille	8096d 03h	/
27	Cleaned up code	rherveille	8096d 03h	/
26	* empty log message *	rherveille	8099d 11h	/
25	Added timing tests to i2c_model. Updated testbench.	rherveille	8127d 08h	/
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	8127d 08h	/
23	* empty log message *	rherveille	8254d 13h	/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8264d 18h	/
21	no message	rherveille	8350d 19h	/
20	Added Appendix A	rherveille	8350d 19h	/
19	Fixed some race conditions in the i2c-slave model. Added debug information. Added headers.	rherveille	8354d 15h	/
18	no message	rherveille	8381d 11h	/
17	C-include file. Initial release	rherveille	8469d 16h	/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8481d 15h	/
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8486d 14h	/