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Rev	Log message	Author	Age	Path
70	Added old uploaded documents to new repository.	root	5735d 02h	/
69	Added old uploaded documents to new repository.	root	5735d 17h	/
68	New directory structure.	root	5735d 17h	/
67	Fixed slave_wait clocked event syntax	rherveille	5768d 20h	/
66	Fixed type iscl_oen instead of scl_oen	rherveille	5783d 19h	/
65	Changed wb_adr_i from unsigned to std_logic_vector	rherveille	5784d 05h	/
64	Added SCL clock synchronization logic Fixed slave_wait signal generation	rherveille	5784d 05h	/
63	Added clock synchronization logic Fixed slave_wait signal	rherveille	5784d 05h	/
62	Fixed synopsys miss spell (synopsis) Fixed cr[0] register width Fixed ! usage instead of ~ Fixed bit controller parameter width to 18bits	rherveille	5784d 19h	/
61	Removed synopsys link; it's not used	rherveille	6439d 07h	/
60	Added missing semicolons ';' on endif	rherveille	6616d 04h	/
59	fixed short scl high pulse after clock stretch	rherveille	6621d 05h	/
58	fixed (n)ack generation	rherveille	6653d 07h	/
57	fixed short scl high pulse after clock stretch fixed slave model not returning correct '(n)ack' signal	rherveille	6653d 07h	/
56	Fixed Tsu:sta timing check. Added Thd:sta timing check.	rherveille	7206d 04h	/
55	Fixed register overwrite issue. Removed full_case pragma, replaced it by a default statement.	rherveille	7207d 06h	/
54	Fixed scl, sda delay.	rherveille	7207d 06h	/
53	Fixed previous fix :) Made a variable vs signal mistake.	rherveille	7503d 04h	/
52	Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.	rherveille	7503d 05h	/
51	Fixed simulation issue when writing to CR register	rherveille	7557d 06h	/

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[/] - Rev 70

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