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Rev Log message Author Age Path
109 Updated memtest code sample:
- Initializes I-cache
- Tests execution from FLASH
- Uses small memory model for faster simulation
ja_rd 4983d 20h /
108 Added new 'small' memory map to SW simulator
(so that memtest simulations can be shorter)
ja_rd 4983d 21h /
107 Adventure demo bootstrap code updated:
- typo fixed
- added basic I-cache initialization code
ja_rd 4987d 19h /
106 SW samples updated:
- Added batch files for running the SW simulation
ja_rd 4987d 20h /
105 SW simulator updated:
- New command line options
- New optional memory map
- Runs on batch mode
- Other features for running uClinux
ja_rd 4987d 20h /
104 FIXED typo in last commit for simulation template ja_rd 4992d 10h /
103 ADDED cache control inputs (unused) to dummy cache ja_rd 4992d 11h /
102 ADDED cache control bits to CP0 status register
ADDED cache control outputs
ja_rd 4992d 11h /
101 FIX: code_rd_vma asserted only after reset is done
ADDED cache control bits to CP0 status register
ADDED cache control outputs
ja_rd 4992d 11h /
100 Obsolete synthesizable template files removed ja_rd 5016d 20h /
99 Obsolete TB template files removed ja_rd 5016d 20h /
98 CPU rd and wr data address buses unified ja_rd 5016d 20h /
97 CPU rd and wr data address buses unified ja_rd 5016d 20h /
96 CPU rd and wr data address buses unified ja_rd 5016d 20h /
95 BUG FIX: cache stub properly handles all kind of cycles now ja_rd 5027d 16h /
94 Pregenerated demo 'hello' files updated ja_rd 5027d 16h /
93 SW simulator supports 'log trigger address' and keyboard input as simulated UART RX.
Project parameters now launch adventure demo automatically
ja_rd 5027d 16h /
92 'hello' demo updated to use new startup files ja_rd 5027d 16h /
91 FIX: startup files can now be used to run from FLASH or BRAM ja_rd 5027d 16h /
90 Added 'Adventure' demo to be run from the DE-1 FLASH ja_rd 5027d 17h /

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