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Rev	Log message	Author	Age	Path
114	ADDED: 1st version of real cache	ja_rd	4948d 07h	/
113	Added clock frequency generic to MPU module template (the generics are used by UART submodules)	ja_rd	4948d 09h	/
112	Updated simulation package for compatibility to new cache	ja_rd	4948d 09h	/
111	Updated 'hello' code sample: - Longer simulated time for compatibility to new cache	ja_rd	4948d 09h	/
110	Updated 'opcodes' code sample: - Longer simulated time for compatibility to new cache	ja_rd	4948d 09h	/
109	Updated memtest code sample: - Initializes I-cache - Tests execution from FLASH - Uses small memory model for faster simulation	ja_rd	4948d 09h	/
108	Added new 'small' memory map to SW simulator (so that memtest simulations can be shorter)	ja_rd	4948d 09h	/
107	Adventure demo bootstrap code updated: - typo fixed - added basic I-cache initialization code	ja_rd	4952d 07h	/
106	SW samples updated: - Added batch files for running the SW simulation	ja_rd	4952d 08h	/
105	SW simulator updated: - New command line options - New optional memory map - Runs on batch mode - Other features for running uClinux	ja_rd	4952d 08h	/
104	FIXED typo in last commit for simulation template	ja_rd	4956d 23h	/
103	ADDED cache control inputs (unused) to dummy cache	ja_rd	4956d 23h	/
102	ADDED cache control bits to CP0 status register ADDED cache control outputs	ja_rd	4956d 23h	/
101	FIX: code_rd_vma asserted only after reset is done ADDED cache control bits to CP0 status register ADDED cache control outputs	ja_rd	4956d 23h	/
100	Obsolete synthesizable template files removed	ja_rd	4981d 08h	/
99	Obsolete TB template files removed	ja_rd	4981d 08h	/
98	CPU rd and wr data address buses unified	ja_rd	4981d 08h	/
97	CPU rd and wr data address buses unified	ja_rd	4981d 08h	/
96	CPU rd and wr data address buses unified	ja_rd	4981d 08h	/
95	BUG FIX: cache stub properly handles all kind of cycles now	ja_rd	4992d 05h	/

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Subversion Repositories ion

[/] - Rev 114

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