OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] - Rev 117

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
117 Updated project doc (still not fully up to date) ja_rd 4987d 15h /
116 Updated demo 'top' file for DE-1 board
- Added reset button debouncing
- Added template for using different clock input
- Uses clock rate generic
ja_rd 4987d 15h /
115 Updated Altera CSV file (pin location file) for DE-1 board
(Added 27MHz clock input)
ja_rd 4987d 17h /
114 ADDED: 1st version of real cache ja_rd 4987d 18h /
113 Added clock frequency generic to MPU module template
(the generics are used by UART submodules)
ja_rd 4987d 19h /
112 Updated simulation package for compatibility to new cache ja_rd 4987d 19h /
111 Updated 'hello' code sample:
- Longer simulated time for compatibility to new cache
ja_rd 4987d 19h /
110 Updated 'opcodes' code sample:
- Longer simulated time for compatibility to new cache
ja_rd 4987d 19h /
109 Updated memtest code sample:
- Initializes I-cache
- Tests execution from FLASH
- Uses small memory model for faster simulation
ja_rd 4987d 19h /
108 Added new 'small' memory map to SW simulator
(so that memtest simulations can be shorter)
ja_rd 4987d 19h /
107 Adventure demo bootstrap code updated:
- typo fixed
- added basic I-cache initialization code
ja_rd 4991d 17h /
106 SW samples updated:
- Added batch files for running the SW simulation
ja_rd 4991d 18h /
105 SW simulator updated:
- New command line options
- New optional memory map
- Runs on batch mode
- Other features for running uClinux
ja_rd 4991d 18h /
104 FIXED typo in last commit for simulation template ja_rd 4996d 09h /
103 ADDED cache control inputs (unused) to dummy cache ja_rd 4996d 09h /
102 ADDED cache control bits to CP0 status register
ADDED cache control outputs
ja_rd 4996d 09h /
101 FIX: code_rd_vma asserted only after reset is done
ADDED cache control bits to CP0 status register
ADDED cache control outputs
ja_rd 4996d 09h /
100 Obsolete synthesizable template files removed ja_rd 5020d 19h /
99 Obsolete TB template files removed ja_rd 5020d 19h /
98 CPU rd and wr data address buses unified ja_rd 5020d 19h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.