OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] - Rev 124

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
124 Fixed typo in python script header comment ja_rd 4865d 01h /
123 Added target to 'hello' makefile for cache-less system simulation ja_rd 4865d 04h /
122 New simulation template for cache-less system
Meant for debug, simulation only
ja_rd 4865d 04h /
121 CPU code reorganized a bit
No new logic, just a few swapped lines and new comments
ja_rd 4865d 19h /
120 Updated main package with lots of wait states for all areas ja_rd 4874d 22h /
119 Updated pre-generated simulation and synthesis demos ja_rd 4874d 22h /
118 Updates sim scripts to include new cache ja_rd 4874d 22h /
117 Updated project doc (still not fully up to date) ja_rd 4874d 23h /
116 Updated demo 'top' file for DE-1 board
- Added reset button debouncing
- Added template for using different clock input
- Uses clock rate generic
ja_rd 4874d 23h /
115 Updated Altera CSV file (pin location file) for DE-1 board
(Added 27MHz clock input)
ja_rd 4875d 01h /
114 ADDED: 1st version of real cache ja_rd 4875d 02h /
113 Added clock frequency generic to MPU module template
(the generics are used by UART submodules)
ja_rd 4875d 03h /
112 Updated simulation package for compatibility to new cache ja_rd 4875d 03h /
111 Updated 'hello' code sample:
- Longer simulated time for compatibility to new cache
ja_rd 4875d 03h /
110 Updated 'opcodes' code sample:
- Longer simulated time for compatibility to new cache
ja_rd 4875d 03h /
109 Updated memtest code sample:
- Initializes I-cache
- Tests execution from FLASH
- Uses small memory model for faster simulation
ja_rd 4875d 03h /
108 Added new 'small' memory map to SW simulator
(so that memtest simulations can be shorter)
ja_rd 4875d 03h /
107 Adventure demo bootstrap code updated:
- typo fixed
- added basic I-cache initialization code
ja_rd 4879d 01h /
106 SW samples updated:
- Added batch files for running the SW simulation
ja_rd 4879d 02h /
105 SW simulator updated:
- New command line options
- New optional memory map
- Runs on batch mode
- Other features for running uClinux
ja_rd 4879d 03h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.