URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

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Rev	Log message	Author	Age	Path
132	Fixed bug in stall logic (stall for back-to-back SW instructions was wrong)	ja_rd	5289d 14h	/
131	change to local system-dependent directory path	ja_rd	5289d 14h	/
130	typo fix	ja_rd	5289d 14h	/
129	updated pregenerated demo ('hello')	ja_rd	5289d 14h	/
128	updated precompiled simulation testbench	ja_rd	5289d 14h	/
127	added SDRAM verilog simulation model to sim script	ja_rd	5289d 14h	/
126	added SDRAM verilog simulation model	ja_rd	5289d 14h	/
125	MPU templates now use the real cache by default	ja_rd	5289d 14h	/
124	Fixed typo in python script header comment	ja_rd	5334d 19h	/
123	Added target to 'hello' makefile for cache-less system simulation	ja_rd	5334d 22h	/
122	New simulation template for cache-less system Meant for debug, simulation only	ja_rd	5334d 22h	/
121	CPU code reorganized a bit No new logic, just a few swapped lines and new comments	ja_rd	5335d 14h	/
120	Updated main package with lots of wait states for all areas	ja_rd	5344d 16h	/
119	Updated pre-generated simulation and synthesis demos	ja_rd	5344d 16h	/
118	Updates sim scripts to include new cache	ja_rd	5344d 16h	/
117	Updated project doc (still not fully up to date)	ja_rd	5344d 17h	/
116	Updated demo 'top' file for DE-1 board - Added reset button debouncing - Added template for using different clock input - Uses clock rate generic	ja_rd	5344d 17h	/
115	Updated Altera CSV file (pin location file) for DE-1 board (Added 27MHz clock input)	ja_rd	5344d 19h	/
114	ADDED: 1st version of real cache	ja_rd	5344d 20h	/
113	Added clock frequency generic to MPU module template (the generics are used by UART submodules)	ja_rd	5344d 21h	/

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[/] - Rev 132

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