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Rev Log message Author Age Path
138 updated simulation & synthesis pre-generated entities
('hello' code sample)		 ja_rd 4926d 03h /
137 Updated TB2 for new cache interface ('unmapped' signal) ja_rd 4926d 03h /
136 Added debug output to synthesizable MPU template, and connected debug signals to LEDs ja_rd 4926d 03h /
135 Added debug output to synthesizable MPU template. ja_rd 4926d 03h /
134 Added 'unmapped access' flag to CPU core, meant for debug mostly.
Eventually this flag will trigger an interrupt.		 ja_rd 4926d 03h /
133 First draft of the SDRAM controller
(Still unused in the code working base)		 ja_rd 4929d 01h /
132 Fixed bug in stall logic
(stall for back-to-back SW instructions was wrong)		 ja_rd 4929d 01h /
131 change to local system-dependent directory path ja_rd 4929d 01h /
130 typo fix ja_rd 4929d 01h /
129 updated pregenerated demo ('hello') ja_rd 4929d 01h /
128 updated precompiled simulation testbench ja_rd 4929d 01h /
127 added SDRAM verilog simulation model to sim script ja_rd 4929d 01h /
126 added SDRAM verilog simulation model ja_rd 4929d 01h /
125 MPU templates now use the real cache by default ja_rd 4929d 01h /
124 Fixed typo in python script header comment ja_rd 4974d 07h /
123 Added target to 'hello' makefile for cache-less system simulation ja_rd 4974d 10h /
122 New simulation template for cache-less system
Meant for debug, simulation only		 ja_rd 4974d 10h /
121 CPU code reorganized a bit
No new logic, just a few swapped lines and new comments		 ja_rd 4975d 01h /
120 Updated main package with lots of wait states for all areas ja_rd 4984d 04h /
119 Updated pre-generated simulation and synthesis demos ja_rd 4984d 04h /

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