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Rev	Log message	Author	Age	Path
141	BUG FIX in cache: cpu stall logic was missing key case 2nd SW in a (cached) row was not being stalled	ja_rd	4887d 03h	/
140	BUG FIX in cpu: MTCx was using Rs as source instead of Rt BUG FIX in cpu: cached sequences of S* were failing, byte_we logic was wrong	ja_rd	4887d 03h	/
139	updated simulation & synthesis pre-generated entities ('hello' code sample)	ja_rd	4887d 21h	/
138	updated simulation & synthesis pre-generated entities ('hello' code sample)	ja_rd	4887d 21h	/
137	Updated TB2 for new cache interface ('unmapped' signal)	ja_rd	4887d 21h	/
136	Added debug output to synthesizable MPU template, and connected debug signals to LEDs	ja_rd	4887d 21h	/
135	Added debug output to synthesizable MPU template.	ja_rd	4887d 21h	/
134	Added 'unmapped access' flag to CPU core, meant for debug mostly. Eventually this flag will trigger an interrupt.	ja_rd	4887d 21h	/
133	First draft of the SDRAM controller (Still unused in the code working base)	ja_rd	4890d 18h	/
132	Fixed bug in stall logic (stall for back-to-back SW instructions was wrong)	ja_rd	4890d 19h	/
131	change to local system-dependent directory path	ja_rd	4890d 19h	/
130	typo fix	ja_rd	4890d 19h	/
129	updated pregenerated demo ('hello')	ja_rd	4890d 19h	/
128	updated precompiled simulation testbench	ja_rd	4890d 19h	/
127	added SDRAM verilog simulation model to sim script	ja_rd	4890d 19h	/
126	added SDRAM verilog simulation model	ja_rd	4890d 19h	/
125	MPU templates now use the real cache by default	ja_rd	4890d 19h	/
124	Fixed typo in python script header comment	ja_rd	4936d 00h	/
123	Added target to 'hello' makefile for cache-less system simulation	ja_rd	4936d 03h	/
122	New simulation template for cache-less system Meant for debug, simulation only	ja_rd	4936d 03h	/

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Subversion Repositories ion

[/] - Rev 141

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