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Rev Log message Author Age Path
144 Added cache setup code to common startup code
Important: the new cache won't work without this		 ja_rd 4820d 22h /
143 'adventure' sample by default will log from 0xb0000000
and simulation length is now longer		 ja_rd 4822d 12h /
142 'Adventure' bootstrap code now enables the cache
(and runs noticeably faster on DE-1 board)		 ja_rd 4822d 12h /
141 BUG FIX in cache: cpu stall logic was missing key case
2nd SW in a (cached) row was not being stalled		 ja_rd 4822d 12h /
140 BUG FIX in cpu: MTCx was using Rs as source instead of Rt
BUG FIX in cpu: cached sequences of S* were failing, byte_we logic was wrong		 ja_rd 4822d 12h /
139 updated simulation & synthesis pre-generated entities
('hello' code sample)		 ja_rd 4823d 06h /
138 updated simulation & synthesis pre-generated entities
('hello' code sample)		 ja_rd 4823d 06h /
137 Updated TB2 for new cache interface ('unmapped' signal) ja_rd 4823d 06h /
136 Added debug output to synthesizable MPU template, and connected debug signals to LEDs ja_rd 4823d 06h /
135 Added debug output to synthesizable MPU template. ja_rd 4823d 06h /
134 Added 'unmapped access' flag to CPU core, meant for debug mostly.
Eventually this flag will trigger an interrupt.		 ja_rd 4823d 06h /
133 First draft of the SDRAM controller
(Still unused in the code working base)		 ja_rd 4826d 03h /
132 Fixed bug in stall logic
(stall for back-to-back SW instructions was wrong)		 ja_rd 4826d 03h /
131 change to local system-dependent directory path ja_rd 4826d 03h /
130 typo fix ja_rd 4826d 03h /
129 updated pregenerated demo ('hello') ja_rd 4826d 04h /
128 updated precompiled simulation testbench ja_rd 4826d 04h /
127 added SDRAM verilog simulation model to sim script ja_rd 4826d 04h /
126 added SDRAM verilog simulation model ja_rd 4826d 04h /
125 MPU templates now use the real cache by default ja_rd 4826d 04h /

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