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Subversion Repositories ion

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Rev	Log message	Author	Age	Path
164	Minor typo fixes in source file	ja_rd	4917d 04h	/
163	SW simulator update: Better disassembly format (hastily tested) New parameters: start address, breakpoint address, whether or not to trap reserved opcodes	ja_rd	4917d 05h	/
162	Fixed stupid mistake in headers (date of project)	ja_rd	4917d 20h	/
161	Added GPL license info to the vhdl headers This project is becoming respectable :)	ja_rd	4917d 20h	/
160	BUG FIX: the cache init code was messing the BSS initialization	ja_rd	4918d 22h	/
159	bug detected but not fixed in cpu (1st instruction after entering user mode is executed in kernel mode)	ja_rd	4919d 05h	/
158	removed file from TB directory which was committed by mistake	ja_rd	4919d 05h	/
157	Bug fix in the missing coprocesor exception. The CPU was triggering a privilege exception for the mtc0 that went into user mode. Logging HDL updated	ja_rd	4920d 15h	/
156	project doc somewhat updated (but still out of date)	ja_rd	4920d 22h	/
155	Temporary warning added to outdated project doc file	ja_rd	4920d 23h	/
154	fixed log trigger address in hello makefile	ja_rd	4921d 00h	/
153	Added R3000 compatible support for kernel/user state: - Implemented KU/IE plus KUp/IEp and KUo/IEo status bits - Updated startup and test code to account for changes - Implemented bit DID NOT TEST rfe instruction (not used in code) - Access to CP0 in user mode triggers 'CpU' trap - Updated software simulator Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.	ja_rd	4921d 00h	/
152	Added R3000 compatible support for kernel/user state: - Implemented KU/IE plus KUp/IEp and KUo/IEo status bits - Updated startup and test code to account for changes - Implemented bit DID NOT TEST rfe instruction (not used in code) - Access to CP0 in user mode triggers 'CpU' trap - Updated software simulator Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.	ja_rd	4921d 00h	/
151	BUG FIX: major bugs fixed in cache module 1.- sram address was wrong (leftover from previous version) 2.- writes to unmapped areas were blocking the cache 3.- Sequence SW,LW produced a RAW data hazard in some cases	ja_rd	4921d 00h	/
150	Bug fix: added missing nop in vacant branch delay slot	ja_rd	4921d 22h	/
149	changed size of simulated flash in opcodes sample code	ja_rd	4921d 22h	/
148	Added optional cache support to 'opcodes' test. Updated simulation length accordingly.	ja_rd	4923d 13h	/
147	SW simulator updated to latest HW revision (plus a few mistakes corrected: wrongly commented out lines, mostly)	ja_rd	4923d 13h	/
146	Added D-Cache setup code to 'adventure' bootstrap code (redundant since common C startup code already does it but...)	ja_rd	4923d 14h	/
145	MAJOR UPDATE: first version of D-Cache	ja_rd	4923d 14h	/

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[/] - Rev 164

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