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Rev Log message Author Age Path
18 pre-generated simulation test bench 'hello world' adapted to
new mult module
ja_rd 4918d 20h /
17 dual-ram-block test bench template updated for new mult module ja_rd 4918d 20h /
16 SW simulator now shows HI and LO in status ja_rd 4918d 21h /
15 Added mult module to sim script ja_rd 4918d 21h /
14 Opcode test now has mul/div tests enabled by default ja_rd 4918d 21h /
13 single-ram-block test bench template updated for new mult module ja_rd 4918d 21h /
12 Adapted multiplier unit from Plasma ja_rd 4918d 21h /
11 SW signed multiplication simulation now lets compiler do the 64-bit arithmetic ja_rd 4919d 08h /
10 Doc update: exceptions as per MIPS standard ja_rd 4919d 22h /
9 Trap handling now works as in the MIPS specs:
EPC points to victim instruction (break/syscall)
Opcode test modified accordingly
ja_rd 4919d 22h /
8 Trap handling now works as in the MIPS specs:
EPC points to victim instruction (break/syscall)
ja_rd 4919d 22h /
7 Traps are now simulated as per MIPS specifications:
EPC point to victim instruction (break/syscall)
ja_rd 4919d 22h /
6 Fix: BREAK now aborts load and jump instructions properly ja_rd 4920d 00h /
5 SW simulator now logs failed assertions instead of quitting ja_rd 4920d 00h /
4 New test for BREAK: abortion of load and jump
Added comment to readme file
ja_rd 4920d 00h /
3 Fixed error in explanation of exceptions ja_rd 4920d 02h /
2 First commit (includes 'hello' demo) ja_rd 4920d 10h /
1 The project and the structure was created root 4922d 13h /

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