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Rev Log message Author Age Path
27 SW simulator updated: now supports CP0 cause register and traps in delay slots ja_rd 4949d 21h /
26 changes in simulation test benches:
Simulation length now configurable from the python script
Console output logged to file, not to modelsim's window		 ja_rd 4950d 00h /
25 opcode test:
HO and LO registers tested along with mul/div and not separately		 ja_rd 4950d 00h /
24 changes in simulation test benches:
Simulation length now configurable from the python script
Console output logged to file, not to modelsim's window		 ja_rd 4950d 00h /
23 Unimplemented instruction are now trapped (barely tested) ja_rd 4950d 00h /
22 FIXED killer bug in instruction decoder for beq & mfc0
Decoding was incomplete and beq was using wrong ALU input		 ja_rd 4950d 22h /
21 Converted multiplier module reset to synchronous ja_rd 4951d 08h /
20 Updated file list ja_rd 4951d 08h /
19 Updated main doc after adding multiplier
Fixed some glaring errors and typos		 ja_rd 4951d 08h /
18 pre-generated simulation test bench 'hello world' adapted to
new mult module		 ja_rd 4951d 10h /
17 dual-ram-block test bench template updated for new mult module ja_rd 4951d 11h /
16 SW simulator now shows HI and LO in status ja_rd 4951d 11h /
15 Added mult module to sim script ja_rd 4951d 11h /
14 Opcode test now has mul/div tests enabled by default ja_rd 4951d 11h /
13 single-ram-block test bench template updated for new mult module ja_rd 4951d 11h /
12 Adapted multiplier unit from Plasma ja_rd 4951d 11h /
11 SW signed multiplication simulation now lets compiler do the 64-bit arithmetic ja_rd 4951d 22h /
10 Doc update: exceptions as per MIPS standard ja_rd 4952d 12h /
9 Trap handling now works as in the MIPS specs:
EPC points to victim instruction (break/syscall)
Opcode test modified accordingly		 ja_rd 4952d 12h /
8 Trap handling now works as in the MIPS specs:
EPC points to victim instruction (break/syscall)		 ja_rd 4952d 12h /

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