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Rev Log message Author Age Path
30 Completed decoding of instructions
(to prevent side effects of invalid opcodes)
ja_rd 5050d 13h /
29 opcode test updated:
supports CP0 cause register and traps in delay slots
tests that traps abort next instruction in all cases
ja_rd 5050d 14h /
28 Core updated:
supports CP0 cause register and traps in delay slots
traps abort next instruction in all cases (incl. jumps/L*/S*)
ja_rd 5050d 14h /
27 SW simulator updated: now supports CP0 cause register and traps in delay slots ja_rd 5050d 16h /
26 changes in simulation test benches:
Simulation length now configurable from the python script
Console output logged to file, not to modelsim's window
ja_rd 5050d 19h /
25 opcode test:
HO and LO registers tested along with mul/div and not separately
ja_rd 5050d 19h /
24 changes in simulation test benches:
Simulation length now configurable from the python script
Console output logged to file, not to modelsim's window
ja_rd 5050d 19h /
23 Unimplemented instruction are now trapped (barely tested) ja_rd 5050d 19h /
22 FIXED killer bug in instruction decoder for beq & mfc0
Decoding was incomplete and beq was using wrong ALU input
ja_rd 5051d 17h /
21 Converted multiplier module reset to synchronous ja_rd 5052d 03h /
20 Updated file list ja_rd 5052d 03h /
19 Updated main doc after adding multiplier
Fixed some glaring errors and typos
ja_rd 5052d 03h /
18 pre-generated simulation test bench 'hello world' adapted to
new mult module
ja_rd 5052d 06h /
17 dual-ram-block test bench template updated for new mult module ja_rd 5052d 06h /
16 SW simulator now shows HI and LO in status ja_rd 5052d 06h /
15 Added mult module to sim script ja_rd 5052d 06h /
14 Opcode test now has mul/div tests enabled by default ja_rd 5052d 06h /
13 single-ram-block test bench template updated for new mult module ja_rd 5052d 06h /
12 Adapted multiplier unit from Plasma ja_rd 5052d 06h /
11 SW signed multiplication simulation now lets compiler do the 64-bit arithmetic ja_rd 5052d 17h /

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