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Rev	Log message	Author	Age	Path
47	Pre-generated simulation test benches updated	ja_rd	4911d 00h	/
46	First version of cache: stub, 1-word cache Stub cache tested on simulation and HW, just a stub Adapted CPU stall logic to 1st version of cache Adapted all other modules for compatibility with cache	ja_rd	4911d 01h	/
45	Fixed some typos in the main doc	ja_rd	4912d 20h	/
44	slite: cleaned up memory allocation/deallocation code	ja_rd	4913d 04h	/
43	added comments to dummy 'cache' stub	ja_rd	4913d 08h	/
42	Added cache stub module, plus related test bench	ja_rd	4915d 03h	/
41	Updated main project doc	ja_rd	4915d 03h	/
40	pre-generated 'hello' demo updated	ja_rd	4915d 03h	/
39	Updated main project doc	ja_rd	4915d 03h	/
38	Minor changes in header comments	ja_rd	4915d 04h	/
37	functions added to package for standard address decoding	ja_rd	4915d 04h	/
36	pre-generated simulation test bench TB1 updated for compatibility to other changes	ja_rd	4915d 04h	/
35	CPU mem_wait logic updated to work with cache	ja_rd	4915d 04h	/
34	default data address moved to 0x80000000 makefiles and readme files updated accordingly	ja_rd	4915d 04h	/
33	bin2hdl now can initialize 16-bit wide memories	ja_rd	4915d 04h	/
32	slite: catch 1-instruction endless loops now can run unattended; will stop at the end of main()	ja_rd	4915d 05h	/
31	Major refactor in slite: supports memory map with more than 1 block indentation made homogeneous unused code removed	ja_rd	4915d 05h	/
30	Completed decoding of instructions (to prevent side effects of invalid opcodes)	ja_rd	4917d 01h	/
29	opcode test updated: supports CP0 cause register and traps in delay slots tests that traps abort next instruction in all cases	ja_rd	4917d 02h	/
28	Core updated: supports CP0 cause register and traps in delay slots traps abort next instruction in all cases (incl. jumps/L/S)	ja_rd	4917d 02h	/

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[/] - Rev 47

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