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Rev Log message Author Age Path
60 Forgot to upload new TB package!!
Without this, simulations don't work...		 ja_rd 5042d 07h /
59 cleaned up top vhdl module of demo
moved reset sync ff chain to top module
updated pre-generated demo file		 ja_rd 5043d 21h /
58 Cleaned up cache stub code ja_rd 5044d 07h /
57 updated precompiled demo:
single 32-bit BROM instead of 4x8-bit		 ja_rd 5044d 09h /
56 synthesis mpu template updated:
BRAM is now one 32-bit-wide block instead of 4 8-bitters
(it is read only)
python script updated accordingly		 ja_rd 5044d 09h /
55 First version of cache: stub, 1-word cache
(forgot to commit new mpu template file)		 ja_rd 5044d 10h /
54 Doc updated
Cache section (2.7) is still missing		 ja_rd 5044d 12h /
53 SW simulator: Major change in logging code.
Changes are logged now with the address of the instruction that caused them.
These changes make the HW simulation TB's life easier.		 ja_rd 5044d 13h /
52 Sim scripts adapted to recent changes ja_rd 5044d 13h /
51 Adapted simulation and synth templates for cache module ja_rd 5044d 13h /
50 New code sample: memtest
Tests external RAM		 ja_rd 5044d 13h /
49 'hello' demo: updated to use new cache module
No longer uses temporary hacks or custom linker script		 ja_rd 5044d 13h /
48 Temporary fix to memory decoding constants ja_rd 5044d 13h /
47 Pre-generated simulation test benches updated ja_rd 5044d 13h /
46 First version of cache: stub, 1-word cache
Stub cache tested on simulation and HW, just a stub
Adapted CPU stall logic to 1st version of cache
Adapted all other modules for compatibility with cache		 ja_rd 5044d 13h /
45 Fixed some typos in the main doc ja_rd 5046d 08h /
44 slite: cleaned up memory allocation/deallocation code ja_rd 5046d 17h /
43 added comments to dummy 'cache' stub ja_rd 5046d 21h /
42 Added cache stub module, plus related test bench ja_rd 5048d 15h /
41 Updated main project doc ja_rd 5048d 15h /

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