OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] - Rev 72

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
72 Fixed stupid bug in SRAM write cycles (setup time violated)
Wait states implemented for SRAM wait and read cycles		 ja_rd 4939d 09h /
71 Doc updated to reflect last changes ja_rd 4939d 21h /
70 updated CodeBlocks project file ja_rd 4939d 21h /
69 Updated simulation scripts
Obsolete sim script removed		 ja_rd 4939d 21h /
68 Updated pre-generated vhdl files ja_rd 4939d 21h /
67 Deprecated files:
Marked three files as unused, to be removed		 ja_rd 4939d 22h /
66 Code samples:
Updated all code samples to use TB2 template and new memory map		 ja_rd 4939d 22h /
65 Fixed io input mux in MPU template 1 ja_rd 4939d 22h /
64 Refactored memory decoding logic
(wait states and read-only attributes unimplemented yet)		 ja_rd 4939d 22h /
63 DE-1 demo top module:
added registers for SD interface, switches and 7-seg display		 ja_rd 4939d 22h /
62 CPU fixed:
fixed bug in EPC load logic relative to mem_wait stalls
parametrized reset and trap vector addresses		 ja_rd 4939d 22h /
61 SW simulator updated:
new mips-1 memory map and trap addresses
slightly better command line argument parsing		 ja_rd 4939d 22h /
60 Forgot to upload new TB package!!
Without this, simulations don't work...		 ja_rd 4939d 22h /
59 cleaned up top vhdl module of demo
moved reset sync ff chain to top module
updated pre-generated demo file		 ja_rd 4941d 11h /
58 Cleaned up cache stub code ja_rd 4941d 22h /
57 updated precompiled demo:
single 32-bit BROM instead of 4x8-bit		 ja_rd 4942d 00h /
56 synthesis mpu template updated:
BRAM is now one 32-bit-wide block instead of 4 8-bitters
(it is read only)
python script updated accordingly		 ja_rd 4942d 00h /
55 First version of cache: stub, 1-word cache
(forgot to commit new mpu template file)		 ja_rd 4942d 00h /
54 Doc updated
Cache section (2.7) is still missing		 ja_rd 4942d 03h /
53 SW simulator: Major change in logging code.
Changes are logged now with the address of the instruction that caused them.
These changes make the HW simulation TB's life easier.		 ja_rd 4942d 03h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.